[en] 'This paper presents a flexible architecture for a GPS receiver using Partial Reconfiguration (PR) on a System on Chip (SoC) device consisting on an FPGA and two ARM cores. With built-in error-correction techniques offered by modern SOCs, this device meets the requirements of a Brazilian nanosatellite for CONASAT constellation. This receiver benefits from PR, thereby increasing system performance, hardware sharing, and power consumption optimization, among others. Additionally, all the advantages favor in-orbit reconfiguration. The proposed architecture, as requested, uses COTS components.'
Research center :
CRTI - Centre de Recherche en Technologie de l'Information
Valderrama, Carlos ; Université de Mons > Faculté Polytechnique > Service d'Electronique et Microélectronique
Language :
English
Title :
Brazilian Nano-satellite with Reconfigurable SOC GNSS Receiver Tracking capability
Publication date :
06 May 2015
Main work title :
FPGAs and Parallel Architectures for Aerospace Applications
Publisher :
Springer International Publishing
ISBN/EAN :
978-3-319-14351-4
Pages :
13
Research unit :
F109 - Electronique et Microélectronique
Research institute :
R300 - Institut de Recherche en Technologies de l'Information et Sciences de l'Informatique R450 - Institut NUMEDIART pour les Technologies des Arts Numériques