A low power 10b, 100 Mspls pipeline ADC on a standard 1.8V 0.18 um CMOS technology

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Berti, Laurent; Delmot, Thierry; Valderrama, Carlos

2005 • Joint Marquiis and 4G-Radio Workshop

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https://hdl.handle.net/20.500.12907/3130

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Disciplines :

Electrical & electronics engineering

Author, co-author :

Berti, Laurent

Delmot, Thierry

Valderrama, Carlos ; Université de Mons > Faculté Polytechnique > Electronique et Microélectronique

Language :

English

Title :

A low power 10b, 100 Mspls pipeline ADC on a standard 1.8V 0.18 um CMOS technology

Publication date :

23 November 2005

Number of pages :

Event name :

Joint Marquiis and 4G-Radio Workshop

Event place :

Castelldefels, Barcelone, Spain

Event date :

2005

Research unit :

F109 - Electronique et Microélectronique

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since 23 December 2010

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