Paper published in a book (Scientific congresses and symposiums)
Parallel Implementation on GPU for EEG Artifact Rejection by Combining FastICA and TQWT
Abidi, Afef; Nouira, Ibtihel; Bedoui, Mohamed Hedi et al.
2019In 2018 IEEE/ACS 15th International Conference on Computer Systems and Applications (AICCSA)
Peer reviewed
 

Files


Full Text
AICCSA.2018.8612838 (1).pdf
Author postprint (455.4 kB)
Download

All documents in ORBi UMONS are protected by a user license.

Send to



Details



Keywords :
correlation coefficient; Electroencephalogram; FastICA-TQWT; Graphical Processing Units; Mean Squared Error; Signal Noise ratio; Correlation coefficient; Fast-ICA; Graphical processing unit (GPUs); Mean squared error; Signal-noise ratio; Computer Networks and Communications; Computer Science Applications; Hardware and Architecture; Signal Processing; Control and Systems Engineering; Electrical and Electronic Engineering
Abstract :
[en] In this work, a new method for removal of ocular and muscular artifacts from Multi-channel electroencephalogram (EEG) is presented in order to obtain a 3D filtered cerebral mapping images. First, a FastICA algorithm of Independent Component Analysis (ICA) is applied in combination with the tunable Q-factor wavelet transform (TQWT), FastICA-TQWT. Then, to show the robustness of this method, a comparison was made between the proposed FastICA-TQWT method and the classical one FastICA-DWT based on three criteria: Mean Squared Error (MSE), correlation coefficient and Signal Noise Ratio (SNR). The results showed that the FastICA-TQWT method gave the highest Signal Noise Ratio and correlation coefficient and the minimum Mean Squared Error. However, the FastICA-TQWT algorithm requires an extremely high computing power. Therefore, the second contribution of this paper is to provide an EEG signal treatment by implementing the hybrid FastICA-TQWT algorithm using a new computing technology designed for a high-performance computing, called Graphical Processing Units (GPUs) using the Compute Unified Device Architecture (CUDA) technology. The performance of the parallel approach running along the GPU was compared to a CPU implementation.
Disciplines :
Electrical & electronics engineering
Author, co-author :
Abidi, Afef  ;  Université de Mons - UMONS > Faculté Polytechnique > Service d'Electronique et Microélectronique ; Technology and Medical Imaging Laboratory, Faculty of Medicine Monastir University of Monastir, Monastir, Tunisia
Nouira, Ibtihel;  Technology and Medical Imaging Laboratory, Faculty of Medicine Monastir University of Monastir, Monastir, Tunisia
Bedoui, Mohamed Hedi;  Technology and Medical Imaging Laboratory, Faculty of Medicine Monastir University of Monastir, Monastir, Tunisia
Valderrama, Carlos Alberto  ;  Université de Mons - UMONS > Faculté Polytechnique > Service d'Electronique et Microélectronique
 These authors have contributed equally to this work.
Language :
English
Title :
Parallel Implementation on GPU for EEG Artifact Rejection by Combining FastICA and TQWT
Publication date :
14 January 2019
Event name :
2018 IEEE/ACS 15th International Conference on Computer Systems and Applications (AICCSA)
Event organizer :
IEEE/ACS
Event place :
Aqaba, Jordan
Event date :
2018
Audience :
International
Main work title :
2018 IEEE/ACS 15th International Conference on Computer Systems and Applications (AICCSA)
Publisher :
IEEE
Peer reviewed :
Peer reviewed
Research unit :
F109 - Electronique et Microélectronique
Research institute :
R300 - Institut de Recherche en Technologies de l'Information et Sciences de l'Informatique
R450 - Institut NUMEDIART pour les Technologies des Arts Numériques
Available on ORBi UMONS :
since 10 May 2022

Statistics


Number of views
10 (4 by UMONS)
Number of downloads
73 (1 by UMONS)

Scopus citations®
 
4
Scopus citations®
without self-citations
4
OpenCitations
 
1
OpenAlex citations
 
4

Bibliography


Similar publications



Contact ORBi UMONS