Profil

Jojczyk Laurent


Main Referenced Co-authors
VALDERRAMA SAKUYAMA, Carlos Alberto  (10)
Da Cunha Possa, Paulo  (6)
Aerssens, Mathieu (1)
Barvaux, Vincent (1)
BUISSERET, Fabien  (1)
Main Referenced Unit & Research Centers
AGIF - Algèbre, Géométrie et Interactions fondamentales (1)
Main Referenced Disciplines
Electrical & electronics engineering (12)
Physics (3)
Computer science (1)
Biochemistry, biophysics & molecular biology (1)
Mathematics (1)

Publications (total 16)

The most downloaded
3 downloads
Buisseret, F., Catinus, L., Grenard, R., Jojczyk, L., Barvaux, V., Fievez, D., & Dierick, F. (2020). Timed Up and Go and Six-Minute Walking Tests with Wearable Inertial Sensor: One Step Further for the Prediction of the Risk of Fall in Elderly Nursing Home People. Sensors. https://hdl.handle.net/20.500.12907/16471
The most cited
28 citations (Scopus®)
Buisseret, F., Catinus, L., Grenard, R., Jojczyk, L., Barvaux, V., Fievez, D., & Dierick, F. (2020). Timed Up and Go and Six-Minute Walking Tests with Wearable Inertial Sensor: One Step Further for the Prediction of the Risk of Fall in Elderly Nursing Home People. Sensors. https://hdl.handle.net/20.500.12907/16471

Buisseret, F., Catinus, L., Grenard, R., Jojczyk, L., Barvaux, V., Fievez, D., & Dierick, F. (2020). Timed Up and Go and Six-Minute Walking Tests with Wearable Inertial Sensor: One Step Further for the Prediction of the Risk of Fall in Elderly Nursing Home People. Sensors.
Peer Reviewed verified by ORBi

Fortounis, G., Chessini Bose, R., Harb, N., Jojczyk, L., Da Cunha Possa, P., & Valderrama, C. (2013). Multi-Core Embedded Systems. In Encyclopedia of Embedded Computing Systems (pp. 350). IGI Global. doi:10.4018/978-1-4666-3922-5

Jojczyk, L., & Valderrama, C. (01 March 2012). M2NoC: Matlab Design Tools for Network on Chip applications. Poster session presented at Matinée des chercheurs (MDC 2012) - Research Fair 2012, Bruxelles, Belgium.

Valderrama, C., Jojczyk, L., Da Cunha Possa, P., & Dondo Gazzano, J. (2011). FPGA and ASIC convergence. Paper presented at VII Southern Programmable Logic Conference - SPL2011, Córdoba, Argentina.

Da Cunha Possa, P., El Hadhri, Z., Jojczyk, L., & Valderrama, C. (2011). Flexible platform for real-time video and image processing. Paper presented at VII Southern Programable Logic Conference - SPL2011, Córdoba, Argentina.

Jojczyk, L., Menezes, D., Aerssens, M., Ndungidi, P., Dualibe, F., & Valderrama, C. (22 March 2011). A 1-Volt Ultra Low-Power True Random Number Generator(TRNG) in a CMOS 65nm Technology. Poster session presented at 6ème édition de la Matinée des Chercheurs (MDC 2011), Mons, Belgium.

Jojczyk, L. (15 December 2010). Design of a low latency spectrum analyzer using the goertzel algorithm with a Network onChip. Paper presented at 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece.

Jojczyk, L., Da Cunha Possa, P., & Valderrama, C. (2010). Design of a low latency spectrum analyser using the Goertzel algorithm with a network on chip. Paper presented at 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece.

Valderrama, C., Jojczyk, L., & Da Cunha Possa, P. (2010). Convergence in Reconfigurable Embedded Systems. Paper presented at 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece.

Jojczyk, L. (07 May 2010). Le Network on Chip: Une architecture pour les applications massivement parallèles et reconfigurables. Paper presented at 2ème Journée de Recherche du Pôle Hainuyer, Mons, Belgium.

Valderrama, C., Jojczyk, L., & Da Cunha Possa, P. (2010). Trends in Reconfigurable Embedded Systems. In Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility Editors M. Khalgui, H-M. Hanisch (pp. 566). IGI Global.

Jojczyk, L. (17 March 2009). A Network on Chip application development pipeline. Poster session presented at Matinée des chercheurs (MDC'2009), Mons, Belgium.

Jojczyk, L. (22 January 2009). Road Network on Chip (RNoC) : Une nouvelle approche du problème d'interconnexion sur puce. Paper presented at EuroDocInfo2009, Université de Mons, Belgium.

Huang, M., Jojczyk, L., & Valderrama, C. (2008). A SDR interconnection architecture proposal for SATCOM applications. Paper presented at IEEE International Design and Test Workshop, Monastir, Tunisia.

Jojczyk, L., & Valderrama, C. (2008). The road-network on chip (R-NoC). Paper presented at Andescon 2008 - Bi-annual Conference of the Andean Council of the IEEE, Cuzco, Peru.

Jojczyk, L. (26 February 2008). Etude de la solution Road-Network on Chip. Poster session presented at Matinée des chercheurs (MDC) 2008, ULB, Unknown/unspecified.

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