P²IP: A novel low-latency Programmable Pipeline Image Processor

Da Cunha Possa, Paulo; Harb, Naim; Valderrama, Carlos

doi:10.1016/j.micpro.2015.06.010

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Article (Scientific journals)

P²IP: A novel low-latency Programmable Pipeline Image Processor

Da Cunha Possa, Paulo; Harb, Naim; Valderrama, Carlos

2015 • In Microprocessors and Microsystems, 39 (2015), p. 529-540

Peer Reviewed verified by ORBi

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https://hdl.handle.net/20.500.12907/41741

DOI
10.1016/j.micpro.2015.06.010

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Details

Research center :

CRTI - Centre de Recherche en Technologie de l'Information

Disciplines :

Computer science
Electrical & electronics engineering

Author, co-author :

Da Cunha Possa, Paulo

Harb, Naim ; Université de Mons > Faculté Polytechnique > Electronique et Microélectronique

Valderrama, Carlos ; Université de Mons > Faculté Polytechnique > Service d'Electronique et Microélectronique

Language :

English

Title :

P²IP: A novel low-latency Programmable Pipeline Image Processor

Publication date :

22 June 2015

Journal title :

Microprocessors and Microsystems

ISSN :

0141-9331

Publisher :

Elsevier, Netherlands

Volume :

Issue :

2015

Pages :

529-540

Peer reviewed :

Peer Reviewed verified by ORBi

Research unit :

F109 - Electronique et Microélectronique

Research institute :

R450 - Institut NUMEDIART pour les Technologies des Arts Numériques

Available on ORBi UMONS :

since 24 June 2015

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